Continuous metal semiconductor alloy via for interconnects

ABSTRACT

A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion.

RELATED APPLICATION

This application is a continuation of U.S. Ser. No. 13/405,739, filedFeb. 27, 2012, which is a continuation of U.S. Ser. No. 12/198,592,filed Aug. 26, 2008, now U.S. Pat. No. 8,169,031, the entire contents ofeach are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a semiconductor structure and a methodof fabricating the same. More particularly, the present inventionrelates to a contact structure including a dielectric material having acontinuous metal semiconductor alloy located within a via, whichstructure is used in interconnecting an underlying semiconductor deviceto external components of a semiconductor chip. The present inventionalso provides a method of fabricating such a continuous metalsemiconductor alloy via-containing contact structure.

BACKGROUND OF THE INVENTION

A semiconductor device, such as, for example, a field effect transistor,is often formed with both back end of the line (BEOL) contacts to thegate and source/drain regions of the device to turn the device on/offand to allow current to flow through the device, respectively, and amiddle of the line (MOL) contact to the body of the device between thesource/drain regions to adjust threshold voltage (Vt).

Traditionally, conductive metals, such as tungsten (W) and aluminum (Al)have been deposited (e.g., by chemical vapor deposition (CVD),sputtering, etc.) into patterned openings (i.e., vias), which arepresent in the dielectric material of the contact (i.e., metallization)structure, to form both MOL and BEOL contacts. Recently, because of itslower electrical resistivity copper and copper alloys, which requireplating, have become the preferred metal for filling the contactopenings in both BEOL and MOL contact (i.e., metallization) structures.

Forming contact structures that include vias that are filled with suchconductive metals to the source/drain regions and the gate of fieldeffect transistors populated using tight pitch design rules introduceprocess and material challenges. For example, it was predicted that20-30 nm vias will show a substantial increase on resistance due to viasidewall roughness and an increase on the filling conductiveresistivity. Overcoming the increased conductor resistivity and the needto maintain smooth via sidewalls led to a proposal in which the viaconductor will be replaced by bundles of carbon nanotubes (CNTs). Whilecarbon nanotubes were shown to have excellent conduction properties,their integration is challenging. For example, the typical synthesistemperature for carbon nanotubes is above 700° C., which is much higherthan the limit of 400° C. imposed by BEOL technology. Additionally, BEOLprocesses such as photoresist removal by O₂ plasma and some PECVDdielectric depositions cannot be carried out in the presence of carbonnanotubes. Furthermore, forming a good contact between the silicide (atthe bottom of the via) and the CNTs, and similarly between the metal (atthe top of the via) and the CNTs is challenging. Avoiding the contactresistance between two different materials, i.e., the via conductor andthe silicide, can further reduce the total access resistance to thedevice being contacted.

SUMMARY OF THE INVENTION

A contact structure is disclosed in which a continuous metalsemiconductor alloy is located within a via contained within adielectric material. The continuous semiconductor metal alloy is indirect contact with an overlying metal line of a first metal levellocated atop the continuous semiconductor metal alloy and at least asurface of each source and drain diffusion region located beneath thecontinuous metal semiconductor alloy. The continuous metal semiconductoralloy can be derived from either a semiconductor nanowire or anepitaxial grown semiconductor material. The term “continuous metalsemiconductor alloy” is used throughout the instant application todenote a silicide or germanide that includes a lower portion that iscontained within an upper surface of each source and drain region, and avertical pillar portion extending upward from the lower portion. Thelower portion of the continuous metal semiconductor alloy and thevertical pillar portion are not separated by a material interface.Instead, the two portions of the continuous metal semiconductor alloyare of unitary construction, i.e., a single piece.

In one embodiment of the invention, the continuous metal semiconductoralloy is derived from semiconductor nanowires that are formed by avapor-liquid solid (VLS) technique, which is a catalyst assisted growthmethod. The temperature used in the VLS technique is typicallycompatible with BEOL processing. The semiconductor nanowires producedusing the VLS technique are very uniform in diameter and smooth on theatomic scale. That is, the semiconductor nanowires maintain the samecross section along a vertical axis. The semiconductor nanowires thatare formed are converted to a continuous metal semiconductor alloy byreacting them with a metal semiconductor alloy forming metal.

The electrical characteristics of the thus formed continuous metalsemiconductor alloy are similar to the bulk material. As such, theinventive continuous metal semiconductor alloy are superior to a viawith a similar dimension that is filled with a conductive metal, suchas, for example, tungsten. With metal filled vias an increase inresistance has been observed due to sidewall roughness and due to themetal being comprised of poly-crystalline grains. The nanowiressidewalls are very smooth and in some cases the metal semiconductoralloy (e.g., silicide or germanide) formed with nanowires can besingle-crystal (one long grain).

Moreover, because of the anisotropic growth of the semiconductornanowires, it is possible, in some embodiments, to form thesemiconductor nanowires prior to depositing the BEOL dielectric. Thisfurther allows for a tighter gate-to-gate pitch than obtainable withconventional vias. Vias are typically tapered with the bottom part beingsmaller than the top part. To avoid hitting the gate line when etching avia, the gate-to-gate spacing is increased to accommodate the larger viadiameter due to tapering. Nanowires fabricated by the VLS technique arevery uniform in diameter and therefore allow a tighter pitch.

It is observed that one advantage of using semiconductor nanowiresinstead of carbon nanotubes is the efficiency of use of available spacefor each case. In fact, a carbon nanotube is a hollow tube and thus onlythe skin contributes to the conduction process (or several concentrictubes in the case of multi-walled carbon nanotubes), while in the caseof continuous metal semiconductor alloys that are derived fromsemiconductor nanowires the whole cylinder is contributing to theconduction process.

In another embodiment of the invention, the continuous metalsemiconductor alloy is formed by epitaxially growing a semiconductormaterial from the surface of at least the source region and drain regionof a semiconductor structure. The epitaxially grown material is singlecrystal, and is seamless. The epitaxially grown semiconductor materialis converted to a continuous metal semiconductor alloy by reacting itwith a metal semiconductor alloy forming metal.

In one embodiment of the invention, a semiconductor structure isprovided that includes:

at least one field effect transistor located on a surface of asemiconductor substrate, the at least one field effect transistorincluding at least a gate electrode, a source region and a drain region;

a continuous metal semiconductor alloy including a lower portion that iscontained within an upper surface of each of the source and drainregions, and a vertical pillar portion extending upwardly from the lowerportion; and

a metal line located on an upper surface of the vertical pillar portionof the continuous metal semiconductor alloy.

In some embodiments of the structure described above, the verticalpillar portion of the continuous metal semiconductor alloy maintains thesame cross section along a vertical axis, i.e., the vertical pillarportion is not tapered and is smooth.

In other embodiments of the invention, the continuous metalsemiconductor alloy forms a conductive path between the source regionand the metal line. In such an embodiment, the conductive path may beohmic (i.e., there are no electrical junctions due to two dissimilarmaterials in contact).

In yet another embodiment of the invention, variations of an electricalpotential along the conductive path are linear, i.e., there are noelectrical junctions due to dissimilar materials.

In a further embodiment of the invention, the vertical pillar portion iscomprised of a single-crystal metal semiconductor alloy. In an evenfurther embodiment, the vertical pillar portion is comprised of a metalsemiconductor alloy nanowire.

A method of forming the above structure is also provided. In oneembodiment of the invention, the above described structure is formed by:

providing at least one field effect transistor on a surface of asemiconductor substrate, the at least one field effect transistorincluding at least a gate electrode, a source region and a drain region;

forming a semiconductor nanowire from at least a surface of the sourceregion and a surface of the drain region;

converting an upper portion of the source region and the drain regionand the semiconductor nanowire into a continuous metal semiconductoralloy, the continuous metal semiconductor alloy includes a lower portionthat is contained within an upper surface of each of the source anddrain regions, and a vertical pillar portion extending upwardly from thelower portion; and

forming a metal line on an upper surface of the vertical pillar portion.

In another embodiment of the invention, the above described structure isformed by:

providing at least one field effect transistor located on a surface of asemiconductor substrate, the at least one field effect transistorincluding at least a gate electrode, a source region and a drain region;

forming a sacrificial dielectric material having via holes that extendto a surface of at least both the source region and the drain region;

forming an epitaxial semiconductor material within the via holes, theepitaxial semiconductor material is in contact with the surface of boththe source region and the drain region;

removing the sacrificial dielectric material;

converting an upper portion of the source region and the drain regionand the epitaxial semiconductor material into a continuous metalsemiconductor alloy, the continuous metal semiconductor alloy includes alower portion that is contained within an upper surface of each of thesource and drain regions, and a vertical pillar portion extendingupwardly from the lower portion; and

forming a metal line on an upper surface of the vertical pillar portion.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1F are pictorial representations (through cross sectionalviews) depicting the basic processing steps in accordance with oneembodiment of the invention; in the illustrated embodiment semiconductornanowires are used.

FIGS. 2A-2G are pictorial representations (through cross sectionalviews) depicting the basic processing steps in accordance with anotherembodiment of the invention; in the illustrated embodiment an epitaxialgrown semiconductor material is used.

FIGS. 3A-3E are pictorial representations (through cross sectionalviews) depicting the basic processing steps that can be used in theembodiment depicted in FIGS. 1A-1F for controlling the nanowire growthorientation.

DETAILED DESCRIPTION OF THE INVENTION

The present invention, which provides a contact structure including acontinuous metal semiconductor alloy contact and a method of fabricatingthe same, will now be described in greater detail by referring to thefollowing discussion and drawings that accompany the presentapplication. It is noted that the drawings that accompany the presentapplication are provided for illustrative purposes only, and, as such,these drawings are not drawn to scale.

In the following description, numerous specific details are set forth,such as particular structures, components, materials, dimensions,processing steps and techniques, in order to provide a thoroughunderstanding of the present invention. However, it will be appreciatedby one of ordinary skill in the art that the invention may be practicedwithout these specific details. In other instances, well-knownstructures or processing steps have not been described in detail inorder to avoid obscuring the invention.

It will be understood that when an element as a layer, region orsubstrate is referred to as being “on” or “over” another element, it canbe directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements may be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

Reference is first made to FIGS. 1A-1F which are pictorialrepresentations (through cross sectional views) illustrating the basicprocessing steps in accordance with one embodiment of the invention. Inthe illustrated embodiment, a continuous metal semiconductor alloy isformed by first growing semiconductor nanowires and thereafterconverting the semiconductor nanowires into the continuous semiconductormetal alloy by reacting the semiconductor nanowires with a metalsemiconductor alloy forming metal.

Specifically, FIG. 1A illustrates an initial structure 10 that can beemployed in this embodiment of the invention. The initial structure 10includes a semiconductor substrate 12 having at least one field effecttransistor (14A and 14B) located on a surface thereof. The at least onefield effect transistor (14A and 14B) includes a gate dielectric 16located on a surface of the semiconductor substrate 12, a gate electrode18 located atop the gate dielectric 16, optionally, at least one spacer20, a source region 22 and a drain region 24. Isolation regions 26 suchas shallow trench isolation regions or local oxidation of siliconisolation regions may also be located within the semiconductor substrate12. In this example substrate 12 is a bulk silicon wafer. It is observedthat the invention could also be applied to a silicon-on-insulator (SOI)wafer. When a SOI wafer is used field effect transistor (14A and 14B)are formed in the SOI layer that is electrically isolated from the restof the substrate by a buried oxide. In every other aspect the structureis effectively the same.

When a plurality of field effect transistors (FETs) are present, some ofthe FETs may be p-type (i.e., PFETs), and the remaining may be n-type(NFETs). When such FETs of different conductivity type are present, anisolation region typically separates the NFETs from the PFETs. In thedrawings, two FETs are shown that share a common diffusion region (i.e.,source or drain).

The initial structure 10 shown in FIG. 1A can be formed utilizingconventional techniques that are well known to those skilled in the art.For example, the initial structure 10 can be formed by any sequence ofdeposition, lithography, and etching. One typical method to form thestructure shown in FIG. 1A is to first form the isolation regions withinthe substrate, then form a stack containing the gate dielectric and gateelectrode by deposition, and thereafter use lithography and etching toform a patterned gate region. The optional spacer may then be formed bydeposition and etching, followed by ion implantation and annealing,which steps are used to form the source and drain regions.Alternatively, a replacement gate process using a dummy gate can beused. So as not to obscure the invention, the details concerning theprocessing of the initial structure 10 shown in FIG. 1A is not providedherein.

The semiconductor substrate 12 of the initial semiconductor structure 10shown in FIG. 1A includes any semiconducting material including, forexample, Si, SiGe, SiGeC, SiC, Ge, Ge alloys, GaAs, InAs, InP and otherIII/V or II/VI compound semiconductors. In addition to these listedtypes of semiconducting materials, the present invention alsocontemplates cases in which the semiconductor substrate 12 is a layeredsemiconductor such as, for example, Si/SiGe, Si/SiC,silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs).In some embodiments of the present invention, it is preferred that thesemiconductor substrate 12 be composed of a Si-containing semiconductormaterial, i.e., a semiconductor material that includes silicon. In yetother embodiments of the present invention, the semiconductor substrate12 is composed of a Ge-containing semiconductor. The semiconductorsubstrate 12 may be doped, undoped or contain doped and undoped regionstherein.

It is also noted that the semiconductor substrate 12 may be strained,unstrained or contain strained regions and unstrained regions therein.The semiconductor substrate 12 may also have a single crystalorientation or alternatively, the substrate 12 may be a hybridsemiconductor substrate that has surface regions having differentcrystallographic orientations. The semiconductor substrate 12 may alsohave one or more isolation regions such as, for example, trenchisolation regions or LOCOS (local oxidation of silicon) isolationregions, located therein.

The semiconductor substrate 12 may have any crystallographic (i.e.,crystal) orientation. In a preferred embodiment, the semiconductorsubstrate 12 is a Si-containing material having a (111), (100) or (110)crystal orientation. In an even more preferred embodiment, thesemiconductor substrate 12 is a Si-containing semiconductor material,preferably silicon, having a (111) crystal orientation. The use ofsilicon having a (111) crystal orientation is preferred in theillustrated embodiment since such a crystal orientation provides a goodcontrol over the vertical growth of semiconductor nanowires. In a highlypreferred embodiment, the semiconductor substrate 12 may include a thinupper layer of (111) Si located on a surface of a lower layer of (100)Si. Such a substrate, as will be described below in reference to FIGS.3A-3E, can be used to control the nanowire growth orientation whileproviding FETs with a (100) oriented surface channel.

The gate dielectric 16 is typically comprised of an insulating oxide,nitride, oxynitride, a high-k dielectric such as hafnium oxide, orcombinations and multilayers thereof. The thickness of the gatedielectric 16 may vary, but typically, the gate dielectric 16 has athickness from 0.5 to 10 nm, with a thickness from 0.5 to 3 nm beingmore typical. The optional at least one spacer 20 is typically comprisedof an insulating oxide, nitride, and/or oxynitride as well. The width ofthe optional at least one spacer 20, as measured at the bottom of thespacer, may vary, with typical ranges being from 20 to 80 nm. The gateelectrode 18 is comprised of any conductive material including, forexample, polysilicon, SiGe, an elemental metal, an alloy including anelemental metal, a metal silicide, a metal nitride or any combinationthereof including multilayers. In one embodiment, the gate electrode 18is comprised of polySi or SiGe. The thickness of the gate electrode 18may vary, with typical thicknesses being from 20 to 200 nm.

In some embodiments, a hard mask (typically comprised of an oxide,nitride and/or oxynitride) is present atop the gate electrode. Anembodiment, including a hard mask atop the gate electrode is not shownin the present invention. It is noted that when a hard mask is presentatop the gate electrode, no nanowire growth atop the hard mask istypically observed. It is also noted that when the gate electrode is notcapped by a semiconductor material such as polySi or SiGe, no nanowiregrowth typically occurs atop the gate electrode.

FIG. 1B illustrates the structure of FIG. 1A after forming catalystparticles (i.e., dots) 28 on the surface of the source region 22 and thedrain region 24 and the gate electrode 18 of each FET. In someembodiments, and prior to catalyst particle (i.e. dot) 28 formation, apreclean process is performed. The preclean process is used to removeany native oxide and/or other contaminants that will not allow thesemiconductor nanowires to mimic the crystal orientation of theunderlying semiconductor material.

The preclean step employed in the present invention includes anytechnique that can remove native oxide and/or other contaminates fromthe surface of the semiconductor substrate. For example, the precleanstep may include, an RCA clean and etching in DHF prior to depositingthe catalyst dots 28. It is also possible to desorb the native oxide byannealing the substrate at a temperature of about 700° C. (or higher) invacuum and then transferring the substrate to a different chamber whilemaintaining vacuum or a non-oxidizing ambient where the catalyst isdeposited in the form of a thin film over the substrate's surface. Thethin catalyst film is then patterned into an array of catalyst dotswhere subsequent growth of nanowires is desired.

The catalyst dots 28 are formed in a grid on the area of thesemiconductor substrate (typically atop the source and drain regionsand, optionally the gate electrode), where subsequent growth ofnanowires is desired. The catalyst dots 28 that can be used in aiding inthe formation of the semiconductor nanowires include, but is not limitedto Au, Ga, Al, Ti, WC (tungsten carbide) and Ni. Preferably, Al, WC, orAu is used as the catalyst dot material.

The catalyst dots 28 used in growing the semiconductor nanowires canalso be formed by other techniques such as evaporation of a metalthrough pores in a mask. The pores in the mask, which define the size ofthe catalyst dots, are typically too small to form with current opticallithographic techniques. As a result, self-assembly methods forpatterning the masks, such as reported in K. Guarini et al. IEDM 2003,p. 541 (2003) and U.S. Patent Application Publication No. 2004/0256662A1, publication date Dec. 23, 2004, from a diblock co-polymer can alsobe used.

Next, and as shown in FIG. 1C, semiconductor nanowires 30 are grownperpendicular to the substrate surface. The growth of the semiconductornanowires 30 is assisted by the catalyst dots 28 and is typicallycarried out by chemical vapor deposition (CVD) or plasma enhancedchemical vapor deposition (PECVD). The growth temperature depends on thesemiconductor nanowire precursor used. For example, when silane (SiH₄)is used to grow silicon nanowires, the growth temperature is typicallyfrom 370° C. to 500° C. The low growth temperature range of 370° C. to500° C. guarantees that only growth enabled by the catalyst takes place(i.e., enabling nanowires growth but not two dimensional deposition overother surfaces). By adding chlorine to SiH₄, the growth temperature canbe raised to above 600° C. while maintaining selectivity (i.e., avoidingdeposition of silicon on dielectric surfaces). For other precursors suchas, for example, silicon tetrachloride (SiCl₄), the growth temperatureis typically from 800° C. to 950° C. The growth rate of thesemiconductor nanowires 30 depends on the growth temperature and the gaspressure in the growth chamber. For example, a typical CVD growth rateof silicon nanowires grown with SiH₄ diluted with H₂ (1:1) at a pressureof 1 torr and a growth temperature of 450° C. is about 7.6 μm/hour. Inone preferred embodiment germane (GeH₄) is used to grow germaniumnanowires. The nanowire growth with germane has two attractive features:(1) Growth is always selective (no deposition on dielectric surfaces).(2) The growth temperature is about 300° C., which is compatible withthe thermal budget imposed by BEOL processing.

The anisotropic growth of the semiconductor nanowires is believed to bebest described by the vapor-liquid-solid (VLS) mechanism. See, forexample, E. I. Givargizov, “Highly Anisotropic Crystals”, KluwerAcademic Publishers, Norwell, Mass., 1986. When the growth is initiated,a metallic-semiconductor (typically a gold-silicon) liquid alloy isformed. With additional supply of semiconductor precursor from the gasphase (e.g., SiH₄), the metallic-semiconductor droplet becomessupersaturated with semiconductor material and the excess semiconductoris deposited at the solid-liquid interface. As a result, the liquiddroplet rises from the original substrate surface to the tip of agrowing nanowire crystal. After semiconductor nanowire 30 growth, themetallic semiconductor liquid alloy will separate during cooling withoutforming a metal semiconductor solid alloy. As a result, the liquid alloyreverts back to a catalyst dot 28 after cooling.

The orientation of each of the semiconductor nanowires 30 formed atopthe source and drain regions matches that of underlying semiconductorsubstrate since it is seeded from that layer. For example, when theunderlying semiconductor substrate has a (111) orientation then thesemiconductor nanowire 30 atop at least the source/drain regions has anorientation that is (111) as it is seeded from the semiconductorsubstrate. The fabrication of the nanowires by VLS growth facilitatesthe formation of nanocrystals with near identical length, size, andorientation.

The semiconductor nanowires 30 that are formed comprise the samesemiconductor material as that found within semiconductor substrate orgate electrode. In a preferred embodiment of the invention, thesemiconductor nanowires 30 are comprised of a Si-containingsemiconductor material, with silicon nanowires being highly preferred.It is noted that nanowire grown is single crystalline, and no apparentinterface exists between the grown semiconductor nanowire and thesubstrate 12 and/or gate electrode 18. It is further observed that thegrown semiconductor nanowires are not tapered and they are smooth.

The semiconductor nanowires 30 that are formed have a length, l, asmeasured from the base of the semiconductor substrate 10 and/or gateelectrode 18 to the tip, from 25 to 20000 nm, with a length from 100 to500 nm being even more typical.

Next, and as shown in FIG. 1D, the reformed catalyst dots 28 are removedfrom the tip of each of the semiconductor nanowires 30 by selectiveetching. For example, aqua regia (a mixture of nitric acid andhydrochloric acid) will selectively etch the catalyst dots 28 from thetip of each of the semiconductor nanowires 30. The surfaces (top andsidewalls) of the semiconductor nanowires 30, the underlyingsemiconductor substrate 12 and optionally the gate electrode 18 arecleaned to remove any native oxide therefrom utilizing a strippingprocess that is well known to those skilled in the art.

FIG. 1D also illustrates the structure after converting thesemiconductor nanowires 30 into a continuous metal semiconductor alloy32. As shown, the continuous semiconductor metal alloy 32 includes alower portion 34 that is contained within an upper surface of eachsource and drain region, and a vertical pillar portion 36 extendingupwardly from the lower portion 34. The lower portion 34 and thevertical pillar portion 36 of the continuous metal semiconductor alloy32 are not separated by a material interface. Instead, the two portions(34 and 36) of the continuous metal semiconductor alloy 32 are ofunitary construction, i.e., a single piece. Since the continuous metalsemiconductor alloy lacks an interface between the various portions,little or no contact resistance is observed.

The converting occurs by a so-called self-aligned silicidation, i.e.,salicidation, process that includes first forming a metal semiconductoralloy forming metal (not shown) across the entire structure after thecatalyst dots have been removed. The metal semiconductor alloy formingmetal includes any metal that is capable of reacting with asemiconductor material to form a silicide or germanide. Examples of suchmetals include, but are not limited to Ti, Ni, Pt, W, Co and Ir. Aconventional alloy additive (such as an anti-agglomeration alloy) canalso be present in the metal semiconductor alloy forming metal.

The metal semiconductor alloy forming metal is formed utilizing anyconformal deposition process including, for example, chemical vapordeposition (CVD), plasma enhanced chemical vapor deposition (PECVD), andatomic layer deposition (ALD). For example when Ni is used the thicknessof the metal semiconductor alloy forming metal may vary, with a rangefrom 3 to 10 nm being typical.

In some embodiments, a diffusion barrier such as TiN or TaN is formedatop the metal semiconductor alloy forming metal utilizing conventionaldeposition techniques that are well known in the art.

A heating, i.e., anneal, step is then performed to cause reactionbetween the metal semiconductor alloy forming metal and the underlyingsemiconductor material. The heating is performed using conditions thatare well known to those skilled in the art. In some embodiments, asingle anneal is used. In another embodiment, a two step anneal is used.The two step anneal is used in instances where excess metal (such as ona sidewall) could consume too much silicon from the source and drainregions. The excess metal is selectively etched after the firstannealing, and a second annealing (usually at an elevated temperature)is applied to form the desired silicide phase (which is usually thelowest resistance phase). For example, when Ni is used rapid thermalannealing (RTA) is used to form the nickel-silicide phase, NiSi. Theannealing temperature is about 400-450° C. A second anneal is not neededin this case since NiSi is the lowest resistance phase.

FIG. 1E illustrates the structure of FIG. 1D after forming a dielectricmaterial 40. The dielectric material 40, which includes any middle ofthe line dielectric material, can be formed utilizing any conventionaldeposition process including, but not limited to CVD, PECVD, chemicalsolution deposition, evaporation, and spin-on coating. Illustrativeexamples of typical middle of the line dielectrics that can be used asdielectric material 40 include SiO₂, a doped or undoped silicate glass,a C doped oxide (i.e., an organosilicate) that includes atoms of atleast Si, C, H and O, a silsesquioxane, a thermosetting polyaryleneether or multilayers thereof. The term “polyarylene” is used in thisapplication to denote aryl moieties or inertly substituted aryl moietieswhich are linked together by bonds, fused rings, or inert linking groupssuch as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl, andthe like.

The dielectric material 40 typically has a dielectric constant that isabout 4.0 or less, with a dielectric constant of about 2.8 or less beingeven more typical. The thickness of the dielectric material 40 may varyso long at it extends to at least an upper surface of the verticalpillar portion 36 of the continuous metal semiconductor alloy 32. Insome embodiments, a conventional planarization process such as, forexample, chemical mechanical polishing and/or grinding, can follow thedeposition of the dielectric material 40. It is noted that thedielectric material 40 fills the spaces between each of the previouslyformed continuous metal semiconductor alloy via contacts.

FIG. 1F illustrates the structure of FIG. 1E after forming a metal line42 of a first metal level. As is shown, each metal line 42 is in contactwith the vertical pillar portion 36 of the underlying continuous metalsemiconductor alloy 32. The metal lines 42 are formed by deposition,patterning and etching. The deposition may include CVD, PECVD,sputtering and plating. The metal lines 42 may comprise any conductivemetal, with W, Cu, Al and alloys of these metals being highly preferred.The thickness of each metal line may vary, with a typically thicknessbeing from 50 to 200 nm.

Reference is now made to FIGS. 2A-2G, which are pictorialrepresentations (through cross sectional views) depicting the basicprocessing steps in accordance with another embodiment of the invention;in the illustrated embodiment an epitaxial grown semiconductor materialis used to form the continuous metal semiconductor alloy contact.

This embodiment of the invention begins by first providing the initialstructure 10 shown in FIG. 2A. It is noted that FIG. 2A is the same asthat shown in FIG. 1A and, as such, no further description concerningthe elements and processes used to form the same are provided. It isfurther noted that like elements in FIG. 2A as in FIG. 1A include thesame reference numerals.

Next, a sacrificial dielectric material 49 is formed which has contactopenings 50 that extend at least down to the surface of thesemiconductor substrate 12 in areas including the source/drain regions.The resultant structure including the sacrificial dielectric material 49having contact openings 50 formed therein is shown, for example, in FIG.2B.

Contact openings to the gate electrode 18 can also be formed as shown.The sacrificial dielectric material 49 is comprised of any insulatingmaterial including, for example silicon oxide, silicon nitride, and/orsilicon oxynitride. Typically, the sacrificial dielectric material 49 isof a different dielectric as compared with the at least one spacer 20.The sacrificial dielectric material 49 is formed utilizing aconventional deposition process such as, for example, CVD and PECVD. Thecontact openings 50 are formed by providing a patterned resist mask atopthe sacrificial dielectric material 49 and etching through the patternedresist mask utilizing a dry etching process (including, for example,reactive ion etching, ion beam etching, plasma etching, or laserablation) or a chemical wet etching.

FIG. 2C illustrates the structure of FIG. 2B after epitaxial growth of asemiconductor material 52. The semiconductor material used comprises thesame material as that of substrate 12, with Si-containing semiconductorsand Ge being highly preferred. The epitaxial growth process is performedutilizing any conventional technique and conditions that are capable offorming an epitaxial semiconductor material. The epitaxial semiconductormaterial 52 that is formed is single crystalline, and seamless. Also,there is no apparent interface between the epitaxial semiconductormaterial 52 and the underlying semiconductor material from which it isgrown.

Since some portion of the epitaxial semiconductor material 52 extendsoutside the contact openings 50 onto an upper surface of the dielectricmaterial (See, FIG. 2C), a planarization process (such as chemicalmechanical planarization and/or grinding) can be used to form the planarstructure shown in FIG. 2D.

Next, the sacrificial dielectric material 49 is removed from thestructure shown in FIG. 2D utilizing any conventional etch back processthat is selective for removing the sacrificial dielectric material 49.An example of such an etch back process that can be used to selectivelyremove the sacrificial dielectric material 49 includes diluted HF whenmaterial 49 is SiO₂, and O₂ plasma when material 49 is an organic film(for example polyimide).

Next, and as shown in FIG. 2E, a metal semiconductor alloy forming metal54 is conformally formed. The metal semiconductor alloy metal 54 that isused in this embodiment of the present invention is the same as thatdescribed above for the embodiment including the semiconductornanowires. The metal semiconductor alloy forming metal 54 is formedutilizing one of the deposition techniques described above in the otherembodiment. An optional diffusion barrier (not shown) can also beformed.

After providing the structure shown in FIG. 2E, a heating step, asdescribed above, is used to cause reaction between the forming metal 54and the epitaxial semiconductor material 52 including the surface of thesemiconductor material 22, 24, and 18, to form the continuous metalsemiconductor alloy contact, which is labeled as 32′. The resultantstructure that is formed after performing the heating step is shown, forexample, in FIG. 2F. As shown, the continuous semiconductor metal alloy32′ includes a lower portion 34′ that is contained within an uppersurface of each source and drain region, and a vertical pillar portion36′ extending upwardly from the lower portion 34′. The lower portion 34′and the vertical pillar portion 36′ of the continuous metalsemiconductor alloy 32′ are not separated by a material interface.Instead, the two portions (34′ and 36′) of the continuous metalsemiconductor alloy 32′ are of unitary construction, i.e., a singlepiece. Since the continuous metal semiconductor alloy lacks an interfacebetween the various portions, little or no contact resistance isobserved.

FIG. 2G illustrates the structure after dielectric material 40 formationand after forming the metal line 42. The dielectric material 40 and themetal line 42 are formed as described in the embodiment including thesemiconductor nanowires.

It should be pointed out that the vertical pillar portion formed in theembodiment shown in FIGS. 1A-F is derived from a semiconductor nanowire,while the vertical pillar portion in the embodiment shown in FIGS. 2A-2Gis derived from an epitaxially grown semiconductor material. The lowerportion of the metal semiconductor alloy in which embodiment is derivedfrom the material within the source/drain regions and, optionally, thegate electrode. It is further observed that the vertical pillar portionand the lower portion (collectively referred to herein as a metalsemiconductor alloy) form a contact that has lower contact resistance ascompared to prior art contacts that includes a separatesilicide/germanide region and a conductively filled metal via.

Reference is now made to FIGS. 3A-3E, which are pictorialrepresentations (through cross sectional views) depicting the basicprocessing steps that can be used in the embodiment depicted in FIGS.1A-1F for controlling the nanowire growth orientation. In theillustrated processing steps, a semiconductor substrate 12′ is formedthat includes a lower layer A comprised of (100) Si and an upper layer Bcomprised of (111) Si. The semiconductor substrate 12′ is formedutilizing a conventional bonding process that is well known to thoseskilled in the art. Next, and as shown in FIG. 3B, isolation regions 26are formed and a patterned hardmask 70 having openings 72 is formed toexpose surfaces of the substrate 12′ (i.e., the upper layer B comprisedof (111) Si) in which the FETs will be formed. The patterned hard mask70 having the openings 72 is formed by first depositing a blanket layerof hardmask material (i.e., an oxide, nitride, and/or oxynitride),forming a patterned resist atop the hard mask material, and etchingthrough the patterned resist utilizing a conventional etching process.FIG. 3C shows the structure after subjecting the exposed areas of theupper layer B comprised of (111) Si to one of oxidation, nitridation andoxynitridation. This step forms the gate dielectric 16 of each FET, oralternatively dielectric film 16 may be removed and a new gatedielectric may be deposited. It is observed that the oxidation formingfilm 16 is meant to consume all of the silicon (111), i.e., film

B, so the FET channel forms in silicon (100). Spacer 20 is then formed,followed by filling the remaining opening with the gate electrode 18 soas to provide the structure shown in FIG. 3D. Next, the patternedhardmask 70 is removed utilizing a conventional hardmask materialstripping process so as to provide the structure shown in FIG. 3E. Thisstructure can be used as the initial structure 10 shown in theembodiment depicted in FIGS. 1A-1F.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

What is claimed is:
 1. A semiconductor structure comprising: a substratecomprising a first semiconductor material having a firstcrystallographic orientation located on portions of a secondsemiconductor material having a second crystallographic orientation thatdiffers from said first crystallographic orientation; at last one fieldeffect transistor located on other portions of said second semiconductormaterial not including said first semiconductor material, wherein saidat least one field effect transistor includes at least a gatedielectric, a gate electrode, a source region and a drain region, saidgate dielectric has a bottom surface in contact with an upper surface ofthe second semiconductor material, an upper surface that is coplanarwith an upper surface of said first semiconductor material, and verticaledges that are in contact with vertical edges of said firstsemiconductor material; a continuous metal semiconductor alloy includinga lower portion that is contained within an upper surface of each ofsaid source and drain regions, and a vertical pillar portion extendingupwardly from said lower portion; and a metal line located on an uppersurface of said vertical pillar portion of the continuous metalsemiconductor alloy.
 2. The semiconductor structure of claim 1 whereinsaid metal semiconductor alloy is a metal silicide.
 3. The semiconductorstructure of claim 1 wherein said metal semiconductor alloy is a metalgermanide.
 4. The semiconductor structure of claim 1 wherein verticalpillar portion of the continuous metal semiconductor alloy maintains thesame cross section along a vertical axis.
 5. The semiconductor structureof claim 1 wherein the continuous metal semiconductor alloy forms aconductive path between the source region and the metal line.
 6. Thesemiconductor structure of claim 5 wherein said conductive path isohmic.
 7. The semiconductor structure of claim 5 wherein said conductivepath exhibits variations in electrical potential that are linear.
 8. Thesemiconductor structure of claim 1 wherein said vertical pillar portionis derived from a single crystal epitaxial semiconductor material. 9.The semiconductor structure of claim 1 wherein said vertical pillarportion is derived from a semiconductor nanowire.
 10. The semiconductorstructure of claim 1 wherein said vertical pillar portion of saidcontinuous metal semiconductor alloy is embedded within a dielectricmaterial.
 11. The semiconductor structure of claim 1 wherein said lowerportion and said vertical pillar portion of said continuous metalsemiconductor alloy are of unitary construction.
 12. The semiconductorstructure of claim 1 wherein no material interface is located betweensaid lower portion and said vertical pillar portion of said continuousmetal semiconductor alloy.
 13. The semiconductor structure of claim 1wherein said lower portion of said continuous metal semiconductor alloyis embedded within said source region and said drain region.
 14. Thesemiconductor structure of claim 1 wherein said lower portion of saidcontinuous metal semiconductor alloy has a width that is greater than awidth of said vertical pillar portion of said continuous metalsemiconductor alloy.
 15. The semiconductor structure of claim 1 whereinsaid at last one field effect transistor comprises spacers located onvertical sidewalls of a patterned gate stack and wherein an edge of saidlower portion of said continuous metal semiconductor alloy does notextend beyond an outermost edge of said spacer.
 16. The semiconductorstructure of claim 15 wherein an outer vertical edge of said verticalpillar portion of said continuous metal semiconductor alloy is separatedfrom said spacer by a dielectric material.